1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a process for producing the same, and in particular to a non-volatile semiconductor memory device making it possible to reduce the electrical resistance of a source diffusion layer, and a process for producing the same.
2. Related Art
Recently, with advances in the compactness, device-speed and integration degree of a semiconductor device, techniques for reducing the region of its chip and improving the density of its wiring have been becoming important.
Concerning a non-volatile semiconductor memory device, however, it is pointed out that the reduction in the area of the chip and the increase in the wiring density result in a problem that the resistance in its wiring portion, in particular its source diffusion layer becomes high.
In other words, a device isolation structure in a semiconductor device is usually formed by oxidizing its silicon substrate selectively according to well-known LOCOS (Local Oxidation of Silicon).
In this manner, however, a portion called bird's beak is generated at the edge of the resultant oxide film in the case wherein the cell structure of the device is made minute. This bird's beak is a structure disadvantageous for making the element minute in the transverse direction of the elements.
When the element is made minute in the transverse direction, a method called trench device isolation is effective. However, a non-volatile semiconductor memory device having a usual trench device isolation has a problem that the resistance of its source diffusion layer becomes high when self-aligned source etching based on anisotropic dry etching is used.
The following will describe a non-volatile semiconductor memory device having a conventional trench device isolation structure. FIG. 1 is a plan view illustrating a non-volatile semiconductor memory device having a common trench device isolation structure, as will also be described later. FIGS. 18A, 18B and 18C are cross sections of a non-volatile semiconductor memory device having a conventional trench device isolation structure, and are cross sections taken on I--I line, II--II line, and III--III line of FIG. 1, respectively.
It is noted that a non-volatile semiconductor memory device having a trench device isolation structure is not prior art. FIGS. 18A to 18C show cross sections of a device if a conventional trench device isolation technique is applied to the non-volatile semiconductor memory device.
As illustrated in FIGS. 18A to 18C, in the conventional trench device isolation structure, the surface of a substrate 1 is stepwise and source diffusion layer 8b are formed on respective surfaces, having different levels, of the substrate 1. Thus, dopant ions constituting the source diffusion layer 8b are not implanted into the side walls of the steps. For this reason, the source diffusion layer 8b becomes an unstable and discontinuous structure, so that their resistance is high. In FIGS. 18A to 18C, numeral 2 denotes a trench device isolation layer, numeral 3 denotes a floating gate, numeral 5 denotes a control gate electrode, numerals 4 and 6 denote a gate insulating film, numeral 8a denotes a drain diffusion layer, numeral 9 denotes an aluminum wiring, numeral 10 denotes a contact hole, numeral 11 denotes an interlayer insulating film, and numeral 12 denotes a side-wall oxide film.
Hitherto, therefore, it has been greatly demanded that the following is developed: a non-volatile semiconductor memory device having a cell structure which can make the resistance of the source diffusion layer 8b low.
As described above, however, in the case of using a trench device diffusion manner suitable for making the memory device minute, the resistance of the source isolation layers 8b is made high for the above-mentioned reason.
If, for example, oblique ion implantation is performed as ion implantation for overcoming the above-mentioned problem, ions can be continuously implanted even into the diffusion layers having different levels.
At this time, however, the ions are implanted in the channel of a transistor, as well. Thus, according to this method, a structure unsuitable for making the memory device minute is made.
Japanese Patent Application Laid-Open No. 8-37285 states that the non-volatile semiconductor memory device disclosed therein makes it possible to generate stable applying-voltage by using self alignment and transversal diffusion. However, this publication does not describe any technique for reducing the resistance of a source diffusion layer.
Japanese Patent Application Laid-Open No. 4-62874 discloses a semiconductor device wherein the surface of a gate electrode and the surface of a device isolation layer are made flat to prevent alignment gap and stabilize on-resistance and withstand voltage of a high-voltage withstanding transistor. However, this publication does not describe any technique for reducing the resistance of a source diffusion layer.